Alerts
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| Signal Name | Description | Condition | Impact |
|---|---|---|---|
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The high voltage (HV) bus goes above the allowed voltage threshold
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The HV bus voltage goes above the allowed voltage threshold
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DCDC functionality may be limited or paused
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The DCDC ENABLE hard line functionality is disabled
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The DCDC ENABLE line functionality is disabled
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The high voltage battery controller (HVBATT) and vehicle controller (VC) cannot force shutdown DCDC by de-asserting the DCDC ENABLE line
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The low voltage (LV) side of the DC link DCDC converter (DCDCB) temperature is too high
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DCDCB LV temperature exceeds the allowed temperature threshold
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DCDC functionality may be limited or paused
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The Power Conversion System (PCS) does not receive one or more DCDC interface Controller Area Network (CAN) messages from the Vehicle Controller (VC)
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The PCS does not receive all expected DCDC interface CAN messages from the VC
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DCDC may not be able to regulate the LV bus voltage requested by the Vehicle Controller (VC)
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PCS does not receive CAN messages from VC that manages the low voltage battery
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PCS does not receive all expected CAN messages from VC that manages the low voltage battery
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DCDC functionality may be limited
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The Power Conversion System (PCS) DC tank Gate Drive Power Supply (GDPS) has not been correctly calibrated
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The DC tank GDPS calibration data is not present in NVM (DcTankGdpsDataMissing=1), or is not validated (DcTankGdpsDataOutOfSpec=1), or is stale (DcTankGdpsDataStale=1)
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The PCS will use inaccurate GDPS calibration data, which may stress the DC tank MOSFETs.
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The Non-Volatile Memory (NVM) server encountered at least one error during initialization
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A step in the NVM server initialization sequence returns an error indication
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NVM record servicing is not possible, making Power Conversion System (PCS2) functionality limited or unavailable
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The AC Line 2 to Neutral voltage has an irrationally high DC offset
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The AC Line 2 to Neutral voltage has an irrationally high DC offset
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DCAC may be limited or unavailable.
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The AC Line 3 to Neutral voltage has an irrationally high DC offset
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The AC Line 3 to Neutral voltage has an irrationally high DC offset
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DCAC may be limited or unavailable.
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The AC Line 1 current has an irrationally high DC offset
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The AC Line 1 current has an irrationally high DC offset
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DCAC may be limited or unavailable.
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The AC Line 2 current has an irrationally high DC offset
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The AC Line 2 current has an irrationally high DC offset
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DCAC may be limited or unavailable.
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The AC Line 3 current has an irrationally high DC offset
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The AC Line 3 current has an irrationally high DC offset
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DCAC may be limited or unavailable.
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The AC Line N current has an irrationally high DC offset
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The AC Line N current has an irrationally high DC offset
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DCAC may be limited or unavailable.
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The Power Conversion System (PCS) detects the DCAC ENABLE digital line is deasserted when DCAC is still commanded to operate
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The PCS detects the DCAC ENABLE digital line is deasserted when DCAC is still commanded to operate
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DCAC converters will be forced shutdown due to the ENABLE line deassertion
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The low voltage (LV) bus goes below the allowed voltage threshold
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The LV bus voltage goes below the allowed voltage threshold
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DCAC may be limited or unavailable.
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The low voltage (LV) bus goes above the allowed voltage threshold
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The LV bus voltage goes above the allowed voltage threshold
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DCAC may be limited or unavailable.
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During AC charging, the measured root mean squared (RMS) voltage across the lines has decreased below the voltage drop threshold when compared to the RMS voltage at the start of AC charging
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The RMS voltage across the lines has decreased below the voltage drop threshold
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Reduced AC charge rate
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The Power Conversion System (PCS) has been placed into manufacturing EOL (End of Line) mode
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EOL mode is enabled from the specific UDS routine
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The PCS should only be operated in this mode during EOL testing. Operating the PCS in this mode outside of EOL testing may result in undefined behavior.
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The temperature of the thermal model for the DCDC low voltage (LV) metal-oxide-semiconductor field-effect transistors (MOSFETs) becomes too high
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The temperature of the thermal model for the DCDC LV MOSFETs rises above its set limit
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The maximum DCDC power may be reduced
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The temperature of the thermal model for the DCDC transformer windings becomes too high
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The temperature of the thermal model for the DCDC transformer windings rises above its set limit
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The maximum DCDC power may be reduced
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